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information in this document is provided solely to enable use of intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. information contained herein supersedes previously published specifications on these devices from intel . ? intel corporation 1999,2000 february 2000 order number: 245425-001 intel a celeron ? processor mobile module: mobile module connector 2 (mmc-2) at 400 mhz, 366 mhz, 333 mhz, and 300 mhz datasheet product features n offering core frequencies of 400 mhz, 366 mhz, 333 mhz, 300 mhz n 1 28k of on-die level 2 cache n 66-mhz processor system bus speed n processor core voltage regulation supports input voltages from 5v to 21v ? above 80 percent peak efficiency n integrated active thermal feedback (atf) system ? acpi specification rev. 1.0 compliant ? internal a/d ? digital signaling (smbus) across the module interface ? programmable trip point interrupt or poll mode for temperature reading n supports a single agp 66-mhz, 3.3v device n thermal transfer plate on the cpu and the intel a 82433bx for heat dissipation n intel 82433bx host bridg e system controller ? dram controller supports edo and sdram at 3.3v ? supports pci clkrun# protocol ? sdram clock support and self-refresh of edo or sdram during suspend mode ? 3.3v only pci bus control, rev 2.1 compliant
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 2 information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life-saving, or life-sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the celeron processor mobile modules may contain design defects or errors known as errata. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained by calling 1-800- 548-4725 or by visiting intel?s web site at http://www.intel.com copyright ? intel corporation1999, 2000. *third-party brands and names are the property of their respective owners.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 3 contents 1.0 introduction ................................ ................... 5 1.1 revision history ................................ .................... 5 2.0 architecture overview .............................. 5 3.0 connector interface ................................ .. 7 3.1 signal definitions ................................ ................... 7 3.1.1 signal list ................................ ................... 8 3.1.2 memory (109 signals) ................................ . 9 3.1.3 agp (60 signals) ................................ ...... 10 3.1.4 pci (58 signals) ................................ ........ 11 3.1.5 geyserville (4 signals) .............................. 12 3.1.6 processor/piix4e/m sideband (8 signals) 13 3.1.7 power management (7 signals) ................ 14 3.1.8 clock (9 signals) ................................ ....... 15 3.1.9 voltages (54 signals) ................................ 16 3.1.10 itp/jtag (9 signals) ................................ 17 3.1.11 miscellaneous (82 signals) ....................... 17 3.2 connector pin assignments ................................ .. 18 3.3 pin and pad assignments ................................ ..... 21 4.0 functional description .............................. 22 4.1 celeron processor mobile module mmc-2 ............ 22 4.2 l2 cache ................................ ............................... 22 4.3 the 82433bx host bridge system controller ....... 22 4.3.1 memory organization ............................... 22 4.3.2 reset strap options ................................ . 23 4.3.3 pci interface ................................ ............. 23 4.3.4 agp interface ................................ ........... 23 4.4 power management ................................ .............. 23 4.4.1 clock control architecture ........................ 23 4.4.2 normal state ................................ ............. 25 4.4.3 auto halt state ................................ .......... 25 4.4.4 stop grant state ................................ ....... 25 4.4.5 quick start state ................................ ....... 25 4.4.6 halt/grant snoop state .......................... 25 4.4.7 sleep state ................................ ............... 25 4.4.8 deep sleep state ................................ ...... 26 4.5 typical pos/str power ................................ ....... 26 4.6 electrical requirements ................................ ........ 27 4.6.1 dc requirements ................................ ..... 27 4.6.2 ac requirements ................................ ...... 28 4.6.2.1 psb clock signal quality specifications and measurement guidelines ............. 29 4.7 voltage regulator ................................ .................. 29 4.7.1 voltage regulator efficiency ..................... 29 4.7.2 control of the voltage regulator ............... 30 4.7.2.1 vol tage signal definition and sequencing ................................ ......... 31 4.7.3 power planes: bulk capacitance requirements ................................ ........................... 32 4.7.4 surge current guidelines ......................... 34 4.7.4.1 slew-rate control: circuit des cription . 36 4.7.4.2 undervoltage lockout: circuit description (v_uv_lockout) ................. 37 4.7.4.3 overvoltage lockout: circuit description (v_ov_lockout) ................................ .... 37 4.7.4.4 overcurrent protection: circuit description ................................ .......... 38 4.8 active thermal feedback ................................ ...... 39 4.9 thermal sensor configuration register ................ 39 5.0 mechanical specification ........................... 39 5.1 module dimensions ................................ ............... 39 5.1.2 pin 1 location of the mmc-2 connector ... 41 5.1.3 printed circuit board thickness ................ 41 5.1.4 height restrictions ................................ ... 42 5.2 thermal transfer plate ................................ .......... 42 5.3 module physical support ................................ ...... 44 5.3.1 module mounting requirements ............... 44 5.3.2 module weight ................................ .......... 45 6.0 thermal specification ................................ . 45 6.1 thermal design power ................................ ......... 45 6.2 thermal sensor setpoint ................................ ....... 45 7.0 labeling information ................................ ... 46 8.0 environmental st andards ......................... 47
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 4 figures figure 1. block diagram of the celeron processor mobile module mmc-2 ................................ ........... 6 figure 2. 400-pin connector footprint pad numbers ......... 21 figure 3. clock control states ................................ ............ 24 figure 4. bclk, tck, and picclk generic clock waveform at the processor core pins ................................ ... 29 figure 5. power-on sequence timing ................................ . 32 figure 6. instantaneous in-rush current model ................... 34 figure 7. instantaneous in-rush current ............................. 35 figure 8. overcurrent protection circuit .............................. 36 figure 9. spice simulation using in-rush protection (example only)) ................................ ................ 37 figure 10. board dimensions with 400-pin connector orientation ................................ ......................... 40 figure 11. board dimensions with 400-pin connector- pin 1 orientation ................................ ......................... 41 figure 12. printed circuit board thickness ......................... 41 figure 13. keep-out zone ................................ ................... 42 figure 14. thermal transfer plate (a) ................................ 43 figure 15. thermal transfer plate (b) ................................ 44 figure 16. standoff holes, board edge clearance, and emi containment ring ................................ .............. 45 figure 17. product tracking information ............................. 46 tables table 1. connector signal summary ................................ .... 7 table 2. memory signal descriptions ................................ ... 9 table 3. agp signal descriptions ................................ ....... 10 table 4. pci signal descriptions ................................ ........ 11 table 5. geyserville descriptions ................................ ....... 12 table 6. processor/piix4e/m sideband signal descriptions ................................ .......................... 13 table 7. power management signal descriptions .............. 14 table 8. clock signal descriptions ................................ ..... 15 table 9. voltage descriptions ................................ ............. 16 table 10. itp/jtag pins ................................ .................... 17 table 11. miscellaneous pins ................................ ............. 17 table 12. connector pin assignments ................................ 18 table 13. connector specifications ................................ .... 22 table 14. configuration straps for the 82433bx host bridge system controller ................................ ............... 23 table 15. clock state characteristics ................................ . 26 table 16. pos/str power ................................ ................. 26 table 17. power supply design specifications ................... 27 table 18. ac specifications at the processor core pins .... 28 table 19. bclk signal quality specifications at the processor core ................................ ................... 29 table 20. typical voltage regulator efficiency ................... 30 table 21. voltage signal definitions and sequences ......... 31 table 22. vr_on in-rush current ................................ ...... 32 table 23. capacitance requirement per power plane ........ 33 table 24. thermal sensor smbus address table .............. 39 table 25. thermal sensor configuration register .............. 39 table 26. thermal design power specification .................. 45 table 27. environmental standards ................................ .... 47
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 5 1.0 introduction this document provides the technical information for integrating the celeron processor mobile module connector 2 (mmc-2) into the latest notebook systems for today?s notebook market. building around this design gives the system manufacturer these advantages: avoids complexities associated with designing high- speed processor core logic boards. provides an upgrade path from previous intel a mobile modules using a standard interface. 1.1 revision history date revision updates 3/1999 1.0 initial release. 5/1999 2.0 new 333-mhz processor speed pos/str corrections esd clarification vr_on and vr_pwrgd correction l2 cache correction power sequence clarification 6/1999 3.0 new 400-mhz processor speed 2/2000 4.0 updated table 24 2.0 architecture overview a highly integrated assembly, the celeron processor mobile module mmc-2 contains the mobile celeron processor core and its immediate system-level support. the celeron processor mobile module mmc-2 offers core speeds of 400 megahertz, 366 megahertz, 333 megahertz, and 300 megahertz. all processor speeds have a 66-megahertz processor system bus speed (psb). the piix4e/m pci/isa bridge is one of two large-scale integrated devices of the intel 440bx agpset. a notebook?s system electronics must include a piix4e/m device to connect to the celeron processor mobile module mmc-2. the piix4e/m provides extensive power management capabilities and supports the intel a 82433bx host bridge, the second integrated device. key features of the 82433bx host bridge include the dram controller, which supports edo at 3.3 volts with a burst read at 7-2-2-2 (60 nanoseconds) or sdram at 3.3 volts with a burst read at 8- 1-1-1 (66 megahertz, cl=2). the 82433bx host bridge also provides a pci clkrun# signal to request piix4e/m to regulate the pci clock on the pci bus. the 82433bx clock enables self refresh mode of edo or sdram during suspend mode and is compatible with smram (c_smram) and extended smram (e_smram) modes of power management. e_smram mode supports write-back cacheable smram up to 1 megabyte. a thermal transfer plate (ttp) on the 82433bx host bridge and the cpu provides heat dissipation and a thermal attach point for the system manufacturer?s thermal solution. an on-board voltage regulator converts the system dc voltage to the processor?s core and i/o voltage. isolating the processor voltage requirements allows the system manufacturer to incorporate different processor variants into a single notebook system. supporting input voltages from 5 volts to 21 volts, the processor core voltage regulation enables an above 80 percent peak efficiency and decouples processor voltage requirements from the system. the celeron processor mobile module mmc-2 also incorporates active thermal feedback (atf) sensing, compliant to the acpi specification rev 1.0 . a system management bus (smbus) supports the internal and external temperature sensing with programmable trip points.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 6 figure 1 illustrates the block diagram of the celeron processor mobile module mmc-2. 400-pin connector cpu volt. reg. pci bus memory bus pclk1 82443bx v_3 hclk0 piix4e/m sidebands atf sense smbus psb mobile celeron processor core r_gtl dclkwr dclkrd agp bus gclki gclko smbus dclko v_dc 5v-21v v_cpupu 2.5v processor core voltage figure 1 . block diagram of the celeron processor mobile module mmc-2
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 7 3.0 connector interface this section provides information on the signal groups and the corresponding pin information. the signals are defined for compatibility with future intel mobile modules. 3.1 signal definitions table 1 provides a list of signals by category and the corresponding number of signals in each category. for proper signal termination, please contact your intel sales representative for further information. table 1 . connector signal summary signal group number of pins memory 109 agp 60 pci 58 processor/piix4e/m sideband 8 geyserville technology 4 power management 7 clocks 9 voltage: v_dc 20 voltage: v_3s 9 voltage: v_5 3 voltage: v_3 16 voltage: vccagp 4 voltage: v_cpupu 1 voltage: v_clk 1 itp/jtag 9 module id 4 ground 45 reserved 33 total 400
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 8 3.1.1 signal list the following notations are used to denote signal type: i input pin o output pin o d open-drain output pin requiring a pull up resistor i d open-drain input pin requiring a pullup resistor i/o d input/open-drain output pin requiring a pullup resistor i/o bi-directional input/output pin the signal description also includes the type of buffer used for a particular signal: gtl+ open-drain gtl+ interface signal pci pci bus interface signals agp agp bus interface signals cmos the cmos buffers are low voltage ttl compatible signals with 3.3-volt outputs with 5.0-volt tolerant inputs.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 9 3.1.2 memory (109 signals) table 2 lists the memory interface signals. table 2 . memory signal descriptions name type voltage description mecc[7:0] i/o cmos v_3 m emory ecc d ata: these signals carry memory ecc data during access to dram. ecc is not supported on the celeron processor mobile module. rasa[5:0]# or csa[5:0]# o cmos v_3 row address strobe (edo): these pins select the dram row. chip select (sdram): these pins activate the sdrams. sdram accepts any command when its cs# pin is active low. casa[7:0]# or dqma[7:0] o cmos v_3 column address strobe (edo): these pins select the dram column. input/output data mask (sdram): these pins act as synchronized output enables during a read cycle and as a byte mask during a write cycle. mab[9:0]# mab[10] mab[12:11]# mab[13] o cmos v_3 memory address (edo/sdram): this is the row and column address for dram. the 82433bx host bridge system controller has two identical sets of address lines (maa and mab#). the module supports only the mab set of address lines. for additional addressing features, please refer to the intel a 440bx agpset datasheet. mwea# o cmos v_3 memory write enable (edo/sdram): mwea# should be used as the write enable for the memory data bus. srasa# o cmos v_3 sdram row address strobe (sdram): when active low, this signal latches row address on the positive edge of the clock. this signal also allows row access and pre- charge. scasa# o cmos v_3 sdram column address strobe (sdram): when active low, this signal latches column address on the positive edge of the clock. this signal also allows column access. cke[5:0] o cmos v_3 sdram clock enable (sdram): sdram clock enable pin. when these signals are deasserted, sdram enters power-down mode. each row is individually controlled by its own clock enable. md[63:0] i/o cmos v_3 memory data: these signals are connected to the dram data bus. they are not terminated on the celeron processor mobile module mmc-2.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 10 3.1.3 agp (60 signals) table 3 lists the agp interface signals. table 3 . agp signal descriptions name type voltage description gad[31:0] i/o agp v_3 agp address/data : the standard agp address and data lines. this bus functions in the same way as the pci ad[31:0] bus. the address is driven with frame# assertion and data is driven or received in following clocks. gc/be[3:0]# i/o agp v_3 agp command/byte enable : this bus carries the command information during agp cycles when pipe# is used. during an agp write, this bus contains byte enable information. the command is driven with frame# assertion and byte enables corresponding to supplied or requested data are driven on the following clocks. gframe# i/o agp v_3 agp frame : not used during agp transactions. remains deasserted by an internal pullup resistor. assertion indicates the address phase of a pci transfer. negation indicates that the cycle initiator desires one more data transfer. gdevsel# i/o agp v_3 agp device select : same function as pci devsel#. it is not used during agp transactions. the 82433bx host bridge system controller drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. girdy# i/o agp v_3 agp initiator ready : indicates the agp compliant target is ready to provide all write data for the current transaction. asserted when the initiator is ready for a data transfer. gtrdy# i/o agp v_3 agp target ready : indicates the agp compliant master is ready to provide all write data for the current transaction. asserted when the target is ready for a data transfer. gstop# i/o agp v_3 agp stop : same function as pci stop#. it is not used during agp transactions. asserted by the target to request the master to stop the current transaction. greq# i agp v_3 agp request : agp master requests for agp. ggnt# o agp v_3 agp grant : same function as on pci. additional information is provided on the st[2:0] bus. pci grant: permission is given to the master to use pci. gpar i/o agp v_3 agp parity : a single parity bit is provided over gad[31:0] and gc/be[3:0]. this signal is not used during agp transactions. pipe# i agp v_3 pipelined request : asserted by the current master to indicate a full width address that is to be queued by the target. the master queues one request each rising clock edge while pipe# is asserted. sba[7:0] i agp v_3 sideband address : this bus provides an additional conduit to pass address and commands to the 82433bx host bridge system controller from the agp master. rbf# i agp v_3 read buffer full : indicates if the master is ready to accept previously requested, low- priority read data. st[2:0] o agp v_3 status bus : provides information from the arbiter to an agp master on what it may do. these bits only have meaning when ggnt is asserted. adstb[b:a] i/o agp v_3 ad bus strobes : provide timing for double-clocked data on the gad bus. the agent providing data drives these signals. these are identical copies of each other. sbstb i agp v_3 sideband strobe : provides timing for a sideband bus. the sba[7:0] (agp master) drives the sideband strobe.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 11 3.1.4 pci (58 signals) table 4 lists the pci interface signals. table 4 . pci signal descriptions name type voltage description ad[31:0] i/o pci v_3 address/data: the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in the following clocks. c/be[3:0]# i/o pci v_3 command/byte enable: the command is driven with frame# assertion and byte enables corresponding to supplied or requested data are driven on the following clocks. frame# i/o pci v_3 frame: assertion indicates the address phase of a pci transfer. negation indicates that the cycle initiator desires one more data transfer. devsel# i/o pci v_3 device select: the 82433bx host bridge drives this signal when a pci initiator is attempting to access dram. devsel# is asserted at medium decode time. irdy# i/o pci v_3 initiator ready: asserted when the initiator is ready for data transfer. trdy# i/o pci v_3 target ready: asserted when the target is ready for a data transfer. stop# i/o pci v_3 stop: asserted by the target to request the master to stop the current transaction. plock# i/o pci v_3 lock: indicates an exclusive bus operation and may require multiple transactions to complete. when lock# is asserted, nonexclusive transactions may proceed. the 82433bx supports lock for cpu initiated cycles only. pci initiated locked cycles are not supported. req[4:0]# i pci v_3 pci request: pci master requests for pci. gnt[4:0]# o pci v_3 pci grant: permission is given to the master to use pci. phold# i pci v_3 pci hold: this signal comes from the expansion bridge; it is the bridge request for pci. the 82433bx host bridge will drain the dram write buffers, drain the processor-to-pci posting buffers, and acquire the host bus before granting the request via phlda#. this ensures that gat timing is met for isa masters. the phold# protocol has been modified to include support for passive release. phlda# o pci v_3 pci hold acknowledge: this signal is driven by the 82433bx host bridge to grant pci to the expansion bridge. the phlda# protocol has been modified to include support for passive release. par i/o pci v_3 parity: a single parity bit is provided over ad[31:0] and c/be[3:0]#. serr# i/o pci v_3 system error : the 82433bx asserts this signal to indicate an error condition. refer to the intel a 440bx agpset datasheet for further information. clkrun# i/o d pci v_3 clock run: an open-drain output and input. the 82433bx host bridge requests the central resource ( piix4e/m ) to start or maintain the pci clock by asserting clkrun#. the 82433bx host bridge tri-states clkrun# upon deassertion of reset (since clk is running upon deassertion of reset). pci_rst# i cmos v_3 reset: when asserted, this signal asynchronously resets the 82433bx host bridge. the pci signals also tri-state, compliant with pci rev 2.1 specifications .
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 12 3.1.5 geyserville (4 signals) table 5 lists the geyserville signal definitions. the celeron processor mobile module mmc-2 does not support geyserville technology. table 5 . geyserville descriptions name type voltage description g_lo/hi# i cmos v_3 geyserville state transition : generated by the piix4e/m, this signal defines a geyserville state change to the geyserville state machine. this signal is not implemented on the module and is defined for upgrade purposes only . g_cpu_stp# i cmos v_3 geyserville cpu_stp# : the cpu_stp# signal gated by the geyserville state machine becomes g_cpu_stp#. this signal is not implemented on the module and is defined for upgrade purposes only. vrchgng# o cmos v_3 voltage changing : a geyserville state machine signal that indicates that the actual state change is in progress ? the vr setpoint has changed and the vr is settling. when this signal deasserts, the new state is sent to the processor. the system electronics will use this signal to generate an sci to force a transition out of deep sleep. this signal is not implemented on the module and is defined for upgrade purposes only. g_sus_stat1# o cmos v_3 g_sus_stat1#: the sus_stat1# signal gated by the geyserville control logic. g_sus_stat1# should be used in place of the sus_stat1# signal in the system electronics design. this signal is not implemented on module and is defined for upgrade purposes only.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 13 3.1.6 processor/piix4e/m sideband (8 signals) table 6 lists the signals for the processor and the piix4e/m sideband signals. the voltage level for these signals is determined by v_cpupu. table 6 . processor/piix4e/m sideband signal descriptions name type voltage description ferr# o cmos v_cpupu numeric coprocessor error : this pin functions as a ferr# signal supporting coprocessor errors. this signal is tied to the coprocessor error signal on the processor and is driven by the processor to the piix4e/m . ignne# i d cmos v_cpupu ignore error : this open-drain signal is connected to the ignore error pin on the processor and is driven by the piix4e/m . init# i d cmos v_cpupu initialization : init# is asserted by the piix4e/m to the processor for system initialization. this signal is an open-drain. intr i d cmos v_cpupu processor interrupt : intr is driven by the piix4e/m to signal the processor that an interrupt request is pending and needs to be serviced. this signal is an open-drain. nmi i d cmos v_cpupu non-maskable interrupt : nmi is used to force a non-maskable interrupt to the processor. the piix4e/m isa bridge generates a nmi when either serr# or iochk# is asserted, depending on how the nmi status and control register is programmed. this signal is an open-drain. a20m# i d cmos v_cpupu address bit 20 mask: when enabled, this open-drain signal causes the processor to emulate the address wraparound at one mb, which occurs on the intel 8086 processor. smi# i d cmos v_cpupu system management interrupt : smi# is an active low synchronous output from the piix4e/m that is asserted in response to one of many enabled hardware or software events. the smi# open-drain signal can be an asynchronous input to the processor. however, in this chip set smi# is synchronous to pclk. stpclk# i d cmos v_cpupu stop clock : stpclk# is an active low synchronous open-drain output from the piix4e/m that is asserted in response to one of many hardware or software events. stpclk# connects directly to the processor and is synchronous to pciclk. when the processor samples stpclk# asserted, it responds by entering a low power state (quick start). the processor will only exit this mode when this signal is deasserted.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 14 3.1.7 power management (7 signals) table 7 lists the power management signals. the sm_clk and sm_data signals refer to the two-wire serial smbus interface. although this interface is currently used solely for the digital thermal sensor, the smbus contains reserved serial addresses for future use. see section 4.9, ?thermal sensor configuration register? for more details. table 7 . power management signal descriptions name type voltage description sus_stat1# i cmos v_3alway 1 suspend status: this signal connects to the sus_stat1# output of piix4e/m. it provides information on host clock status and is asserted during all suspend states. vr_on i cmos v_3 vr_on: voltage regulator on. this 3.3-v (5.0v tolerant) signal controls the operation of the voltage regulator. vr_on should be generated as a function of the piix4e/m susb# signal which is used for controlling the ?suspend state b? voltage planes. this signal should be driven by a digital signal with a rise/fall time of less than or equal to 1 us. refer to section 4.7.2.1 ??voltage signal definitions and sequences.? (vil (max)=0.4v, vih (min)=3.0v.) vr_pwrgd o v_3 vr_pwrgd: this signal is driven high by the module to indicate that the voltage regulator is stable. the signal is pulled low using a 100k resistor when inactive. it can be used in some combination to generate the system pwrgood signal. bxpwrok i cmos v_3 power ok to bx: this signal must go active 1 ms after the v_3 power rail is stable, and 1 ms prior to deassertion of pcirst#. sm_clk i/o d cmos v_3 serial clock: this clock signal is used on the smbus interface to the digital thermal sensor. sm_data i/o d cmos v_3 serial data: open-drain data signal on the smbus interface to the digital thermal sensor. atf_int# o d cmos v_3 atf interrupt: this signal is an open-drain output signal of the digital thermal sensor. note: 1. v_3always is a 3.3-v supply. it is generated whenever v_dc is available and supplied to piix4e/m resume well.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 15 3.1.8 clock (9 signals) table 8 li sts the clock signals. table 8 . clock signal descriptions name type voltage description pclk i pci v_3 pci clock in: pclk is an input to the module and is one of the system?s pci clocks. this clock is used by all of the 82433bx host bridge logic in the pci clock domain. this clock is stopped when the piix4e/m pci_stp# signal is asserted and/or during all suspend states. hclk[1:0] i cmos v_clk host clock in: these clocks are inputs to the module from the ck97-m clock source. the processor and the 82433bx host bridge system controller use hclk[0]. this clock is stopped when the piix4e/m cpu_stp# signal is asserted and/or during all suspend states. dclko o cmos v_3 sdram clock out: a 66-mhz sdram clock reference generated internally by the 82433bx host bridge system controller onboard pll. it feeds an external buffer that produces multiple copies for the so-dimms. dclkrd i cmos v_clk sdram read clock: feedback reference from the sdram clock buffer. the 82433bx host bridge system controller uses this clock when reading data from the sdram array. this signal is not implemented on the module. dclkwr i cmos v_clk sdram write clock: feedback reference from the sdram clock buffer. the 82433bx host bridge system controller uses this clock when writing data to the sdram array. gclkin i cmos v_3 agp clock in: the gclkin input is a feedback reference from the gclko signal. gclko o cmos v_3 agp clock out: this signal is generated by the 82433bx host bridge system controller onboard pll from the hclk0 host clock reference. the frequency of gclko is 66 mhz. the gclko output is used to feed both the pll reference input pins on the 82433bx host bridge system controller and the agp device. the board layout must maintain complete symmetry on loading and trace geometry to minimize agp clock skew. fqs o cmos v_clk frequency select: this output signal provides the status of the host clock frequency to the system electronics. this signal is static and is pulled either low or high to the v_clk voltage supply through a 10-k w resistor. this module is designed for the 66-mhz strapping option shown below. fqs=0 indicates 66 mhz fqs=1 indicates 100 mhz (for future intel mobile modules)
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 16 3.1.9 voltages (54 signals) table 9 lists the voltage signal definitions. table 9 . voltage descriptions name type number of pins description v_dc i 20 dc input: 5v-21v v_3s i 9 susb# controlled 3.3v: this rail is not used on the module. however, it is a power managed 3.3-v supply. an output of the voltage regulator on the system electronics. this rail is off during str, std, and soff. v_5 i 3 susc# controlled 5v: power managed 5.0-v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. v_3 i 16 susc# controlled 3.3v: power managed 3.3-v supply. an output of the voltage regulator on the system electronics. this rail is off during std and soff. vccagp i 4 agp i/o voltage : this voltage rail is not implemented on module and is defined for upgrade purposes only. intel recommends that this voltage rail be connected to v_3 on the system electronics. v_cpupu o 1 processor i/o ring: driven by the module to power processor interface signals such as the piix4e/m open-drain pullups for the processor/ piix4e/m sideband signals. v_clk o 1 processor clock rail: driven by the module to power ck100-m vddcpu rail.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 17 3.1.10 itp/jtag (9 signals) table 10 lists the itp/jtag signals, which the system manufacturer can use to implement a jtag chain and an itp port if desired. table 10 . itp/jtag pins name type voltage description tdo o v_cpupu jtag test data out: serial output port. tap instructions and data are shifted out of the processor from this port. tdi i v_cpupu jtag test data in: serial input port. tap instructions and data are shifted into the processor from this port. tms i v_cpupu jtag test mode select: controls the tap controller change sequence. tclk i v_cpupu jtag test clock: testability clock for clocking the jtag boundary scan sequence. trst# i v_cpupu jtag test reset: asynchronously resets the tap controller in the processor. fs_reset# o gtl+ processor reset: processor reset status to the itp. vtt o v_core gtl+ termination voltage: used by the poweron pin on the itp debug port to determine when target system is on. poweron pin is pulled up using a 1-k w resistor to vtt. fs_preq# i v_cpupu debug mode request: driven by the itp and makes request to enter debug mode. fs_prdy# o gtl+ debug mode ready: driven by the processor and informs the itp that the processor is in debug mode. note: dbrest# (reset target system) on the itp debug port can be ?logically anded? with vr_pwrgd to piix4e/m?s pwrok. 3.1.11 miscellaneous (82 signals) table 11 lists the miscellaneous signal pins. table 11 . miscellaneous pins name type number description module id[3:0] o cmos 4 module revision id : these pins track the revision level of the celeron processor mobile module mmc-2. a 100-k pullup resistor to v_3s must be placed on the system electronics for these signals. see section 7.0, ?labeling information? for more information. ground i 45 ground. reserved rsvd 33 unallocated reserved pins and should not be connected.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 18 3.2 connector pin assignments table 12 lists the signals for each pin of the connector to the system electronics. refer to section 3.3, ?pin and pad assignments? for the pin assignments of the pads on the connector. table 12 . connector pin assignments pin number row a row b row c row d row e 1 sba5 adstbb gnd gad31 sba7 2 gad25 gad24 sba6 sba4 sba0 3 gad30 gad29 gad26 gad27 gnd 4 gnd vccagp gad4 gad6 gad8 5 rbf# gad1 gad3 gad5 gc/be0# 6 bxpwrok reserved gad2 adstba gnd 7 md0 md1 v_3 clkrun# gad7 8 md2 md33 gnd md32 gad0 9 md36 md4 md3 md35 md34 10 md7 md38 md37 md6 md5 11 md41 md42 md40 md39 md8 12 md43 md11 gnd md10 md9 13 md14 md45 md44 md13 md12 14 mecc4 mecc0 md15 md47 md46 15 scasa# mwea# mecc5 reserved gnd 16 gnd mid1 dqma0 dqma1 reserved 17 v_3 dqma4 mid0 dqma5 csa0# 18 csa1# csa2# csa4# csa3# gnd 19 srasa# csa5# mab0# mab1# reserved 20 reserved reserved mab2# reserved mab3# 21 reserved mab4# gnd reserved mab6# 22 reserved reserved mab5# reserved mab7# 23 mab8# reserved reserved mab9# mab10 24 reserved mab11# mab12# reserved dclko 25 mab13 v_3 gnd cke0 dclkrd 26 cke1 mid2 cke3 cke4 gnd 27 cke5 cke2 mid3 g_cpu_stp# vrchgng# 28 reserved g_lo/hi# dqma2 dclkwr gnd 29 gnd vtt reserved fs_preq# dqma3 30 fs_reset# v_3 md26 gnd md25 31 fs_prdy# gnd md58 md57 md60 32 g_sus_stat1# smclk tdo tclk ferr#
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 19 pin number row a row b row c row d row e 33 reserved smdat tdi tms ignne# 34 reserved fqs reserved trst# atf_int# 35 reserved v_5 v_3s v_3s v_3s 36 v_cpupu v_5 v_3s v_3s v_3s 37 v_clk v_5 v_3s v_3s v_3s 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc pin number row f row g row h row j row k 1 greq# gnd pipe# sba3 gnd 2 st0 st1 sba1 sbstb gclki 3 ggnt# st2 sba2 gnd gclko 4 gad13 gstop# gad16 gad20 gad23 5 gad12 gpar gad18 gad17 gc/be3# 6 gad10 gad15 gframe# gnd gad22 7 gad11 gc/be1# gtrdy# gc/be2# gad21 8 gad9 gad14 gdevsel# girdy# gad19 9 gnd vccagp gnd vccagp gad28 10 ad0 ad4 ad2 ad3 ad1 11 gnd c/be0# ad6 gnd ad5 12 vccagp ad10 ad7 ad8 ad9 13 mecc1 ad13 gnd ad12 ad11 14 serr# par ad15 c/be1# ad14 15 ad16 trdy# stop# devsel# plock# 16 ad19 gnd ad17 gnd ad18 17 ad23 ad30 ad24 c/be2# ad21 18 ad27 ad22 c/be3# ad26 pclk 19 pci_rst# gnd ad20 ad28 gnd 20 reserved phold# ad31 ad29 ad25 21 irdy# frame# gnd req1# req0# 22 gnd gnt2# req2# req3# gnt3# 23 gnt1# gnt4# gnt0# req4# gnd 24 gnd phlda# gnd v_3 md59 25 dqma6 mecc7 md50 md51 md54
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 20 pin number row f row g row h row j row k 26 mecc2 md48 md18 md52 md24 27 dqma7 md16 md19 gnd md23 28 mecc6 md17 md21 md53 md55 29 mecc3 md49 md20 md22 md56 30 md27 md28 gnd md62 md63 31 gnd md29 md61 md30 md31 32 smi# intr vr_on gnd gnd 33 nmi sus_stat1# vr_pwrgd gnd hclk0 34 a20m# stpclk# init# gnd gnd 35 v_3 v_3 v_3 gnd hclk1 36 v_3 v_3 v_3 gnd gnd 37 v_3 v_3 v_3 v_3 v_3 38 reserved reserved reserved reserved reserved 39 v_dc v_dc v_dc v_dc v_dc 40 v_dc v_dc v_dc v_dc v_dc
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 21 3.3 pin and pad a ssignments the mmc-2 connector has 400 pins, a 1.27-millimeter pitch, and has a bga style surface mount. refer to section 5.1.4, ?height requirements? for connector size information. figure 2 shows the pad assignments of the mmc-2 connector. 400-pin connector oem pad assignments (viewed from secondary side) k a 1 40 figure 2 . 400-pin connector footprint pad numbers
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 22 table 13 summarizes some of the key specifications for the connector. table 13 . connector specifications parameter condition specification material contact copper alloy housing thermo plastic molded compound: lcp electrical current 0.5a voltage 50 vac insulation resistance 100 m w minimum at 500 vdc termination resistance 10 m w maximum capacitance 5 pf maximum per contact mechanical mating cycles 50 cycles connector mating force 2.0 oz maximum per contact contact unmating force 1.5 oz minimum per contact 4.0 functional description 4.1 celeron processor mobile module mmc-2 the celeron processor mobile module mmc-2 offers core speeds of 400 megahertz, 366 megahertz, 333 megahertz, and 300 megahertz. all processor speeds have a 66- megahertz psb speed. 4.2 l2 cache the on-die l2 cache is 128 kilobytes, is four-way set associative, and runs at the speed of the processor core. 4.3 the 82433bx host bridge system controller intel?s 82433bx host bridge system controller is a highly integrated device that combines the bus controller, the dram controller, and the pci bus controller into one component. the 82433bx host bridge has multiple power management features designed specifically for notebook systems such as: clkrun#, a feature that enables controlling of the pci clock on or off. the 82433bx host bridge suspend modes, which include suspend-to-ram (str), suspend-to-disk (std), and power-on-suspend (pos). system management ram (smram) power management modes, which include compatible smram (c_smram) and extended smram (e_smram). c_smram is the traditional smram feature implemented in all intel pci chipsets. e_smram is a new feature that supports write-back cacheable smram space up to 1 megabyte. to minimize power consumption while the system is idle, the internal 82433bx host bridge clock is turned off (gated off) when there is no processor and pci activity. this is accomplished by setting the g_clk enable bit in the power management register in the 82433bx through the system bios. 4.3.1 memory organization the memory interface of the 82433bx host bridge is available at connector. this allows for the following: one set of memory control signals, sufficient to support up to three so-dimm sockets and six banks of sdram at 66 megahertz. one cke signal for each bank. memory features not supported by the 82433bx host bridge system controller standard mmc-2 mode are: support for eight banks of memory. second set of memory address lines (maa[13:0]). dram technologies supported by the 82433bx host bridge system controller include edo and sdram. these memory types may not be mixed in the system, so that all dram in all rows (ras[5:0]#) must be of the same technology. the 82433bx host bridge system controller targets 60 nanoseconds edo drams and 66-megahertz sdrams. the celeron processor mobile module mmc-2?s clocking architecture supports the use of sdram. tight timing requirements of the 66-megahertz sdram clocks allow all host and sdram clocks to be generated from the same clocking architecture. for complete details about using sdram memory and for trace length guidelines, refer to the mobile pentium? ii processor / 82433bx agpset advanced platform recommended design and debug practices. refer
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 23 to the intel a 440bx agpset datasheet for details on memory device support, organization, size, and addressing . 4.3.2 reset strap options several strap options on the memory address bus define the behavior of the celeron processor mobile module mmc-2 after reset. other straps are allowed to override the default settings. table 14 shows the various straps and their implementation. table 14 . configuration straps for the 82433bx host bridge system controller signal function module default setting optional override on system electronics mab[12]# host frequency select no strap - 66 mhz default. none mab[11]# in order queue depth no strap - maximum queue depth is set, i.e. 8. none mab[10] quick start select strapped high on the module for quick start mode. none mab[9]# agp disable no strap - agp is enabled. pull up this signal to disable the agp interface. mab[7]# mm config no strap - standard mmc-2 mode. none mab[6]# host bus buffer mode select strapped high on the module for mobile psb buffers. none 4.3.3 pci interface the pci interface of the 82433bx host bridge is available at the connector. the 82433bx host bridge supports the pci clockrun protocol for pci bus power management. in this protocol, pci devices assert the clkrun# open-drain signal when they require the use of the pci interface. refer to the pci mobile design guide for complete details on the pci clockrun protocol. the 82433bx host bridge is responsible for arbitrating the pci bus. with the mmc-2 connector, the 82433bx host bridge can support up to five pci bus masters. there are five pci request/grant pairs, req[4:0]# and gnt[4:0]#, available on the connector to the manufacturer?s system electronics. the pci interface on the mmc-2 connector is 3.3 volts only. five-volt pci devices are not supported such as all devices that drive outputs to a 5 vt nominal v oh level. the 82433bx host bridge system controller is compliant with the pci 2.1 specification , which improves the worst case pci bus access latency from earlier pci specifications. the 82433bx host bridge supports only mechanism #1 for accessing pci configuration space, as detailed in the pci specification. this implies that signals ad[31:11] are available for pci idsel signals. however, since the 82433bx host bridge is always device #0, ad11 will never be asserted during pci configuration cycles as an idsel. the 82433bx reserves ad12 for the agpbus. thus, ad13 is the first available address line usable as an idsel. intel recommends that ad18 be used by the piix4e/m. 4.3.4 agp interface the 82433bx host bridge system controller is compliant with the agp interface specification rev 1.0 , which supports an asynchronous agp interface coupling to the 82433bx core frequency. the agp interface can achieve real data throughput in excess of 500 megabytes per second using an agp 2x graphics device. actual bandwidth may vary depending on specific hardware and software implementations. 4.4 power management 4.4.1 clock control architecture the clock control architecture is optimal for notebook designs. the clock control architecture consists of seven different clock states: normal, stop grant, auto halt, quick start, halt/grant snoop, sleep, and deep sleep states. the auto halt state provides a low-power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a very low-power, low-exit latency clock state that can be used for hardware controlled ?idle? states. the deep sleep state provides an extremely low power state that can be used for power-on- suspend states, which is an alternative to shutting off the processor?s power. the exit latency of the deep sleep state has been reduced to 30 microseconds. the stop grant and sleep states are not available on the celeron processor mobile modules these states are intended for desktop or server systems. the stop grant state and the quick start
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 24 clock state are mutually exclusive. for example, a strapping option on signal a15# chooses which state is entered when the stpclk# signal is asserted. strapping the a15# signal enables the quick start state to ground at reset. otherwise, asserting the stpclk# signal puts the processor into the stop grant state. the stop grant state is useful for smp platforms and is not supported on the celeron processor mobile module. the quick start state is available on the module and provides a significantly lower power level. figure 3 provides an illustration of the clock control architecture. state transitions not shown in figure 3 are neither recommended nor supported halt/grant snoop normal state hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qse and sga snoop occurs snoop serviced stpclk# and qse and sga (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qse and sga hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qse and sga !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qse bclk stopped bclk on and qse halt break ? a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi# hlt ? hlt instruction executed hs ? processor halt state qse ? quick start state enabled sga ? stop grant acknowledge bus cycle issued stop break ? binit#, flush#, reset# intel mobile modules do not support the shaded clock states figure 3 . clock control states
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 25 4.4.2 normal state this is the normal operating mode where the processor?s core clock is running and the processor is actively executing instructions. 4.4.3 auto halt state this is a low-power mode entered by the processor through the execution of the hlt instruction. the power level of this mode is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush#, or smi#). asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the stop grant state or the quick start state, where a stop grant acknowledge bus cycle will be issued. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. the smi# (system management interrupt) is recognized in the auto halt state. the return from the smi handler can be to either the normal state or the auto halt state. see the intel ? architecture software developer?s manual, volume iii: system programmer?s guide for more information. no halt bus cycle is issued when returning to the auto halt state from system management mode (smm). the flush# signal is serviced in the auto halt state. after flushing the on-chip, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 4.4.4 stop grant state this state is not available on intel mobile modules. the processor enters this mode with the assertion of the stpclk# signal when it is configured for stop grant state (via the a15# strapping option). the processor is still able to respond to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the deassertion of the stpclk# signal, or the occurrence of a stop break event (a binit#, flush#, or reset# assertion). the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been deasserted. reset# assertion will cause the processor to immediately initialize itself. however, the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. while in the stop grant state, assertions of smi#, init#, intr, and nmi (or lint[1:0]) will be latched by the processor. these latched events will not be serviced until the processor returns to the normal state. only one of each event will be recognized upon return to the normal state. 4.4.5 quick start state this is a mode entered by the processor with the assertion of the stpclk# signal when it is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the psb priority device. because of its snooping behavior, quick start can only be used in single processor configurations. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to flush# and binit# assertions. in the quick start state, the processor will not respond properly to any input signal other than stpclk#, reset#, or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. 4.4.6 halt/grant snoop state the processor will respond to snoop transactions on the psb while in the auto halt, stop grant, or quick start state. when a snoop transaction is presented on the system bus, the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the psb is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state (except for those signal transitions that are required to perform the snoop). 4.4.7 sleep state this state is not available on intel mobile modules. the sleep state is a very low-power state in which the processor maintains its context and the phase locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 26 grant state the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# signal is not recognized in the normal state or the auto halt state. the processor can be reset by the reset# signal while in the sleep state. if reset# is driven active while the processor is in the sleep state, then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly initializes itself. input signals (other than reset#) may not change while the processor is in the sleep state or transitioning into or out of the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. while in the sleep state the processor can enter its lowest power state, the deep sleep state. removing the processor?s input clock puts the processor in the deep sleep state. picclk may be removed in the sleep state. 4.4.8 deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. stopping the bclk input to the processor enters the deep sleep state, while it is in the sleep state or the quick start state. for proper operation, the bclk input should be stopped in the low state. the processor will return to the sleep state or the quick start state from the deep sleep state when the bclk input is restarted. due to the pll lock latency, there is a 30- millisecond delay after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on when transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior. table 15 . clock state characteristics clock state exit latency processor power snooping system uses normal n/a varies yes normal program execution. auto halt approximately 10 bus clocks 1.2w yes s/w controlled entry idle mode. stop grant 1 10 bus clocks 1.2w yes h/w controlled entry/exit mobile throttling. quick start through snoop , to halt/grant snoop state: immediate through stpclk #, to normal state: 10 bus clocks 0.5w yes h/w controlled entry/exit mobile throttling. halt/grant snoop a few bus clocks after the end of snoop activity. not specified yes supports snooping in the low power states. sleep 1 to stop grant state 10 bus clocks 0.5w no h/w controlled entry/exit desktop idle mode support. deep sleep 30 ms 150 mw no h/w controlled entry/exit mobile powered-on suspend support. notes: 1. intel mobile modules do not support shaded clock control states. 2. not 100% tested. specified at 50 c by design and characterization. 4.5 t ypical pos and str power table 16 shows the typical pos and str power values. table 16 . pos and str power state typical mmc-2 power pos 0.475w str 0.018w note : these are average values of measurement and are guidelines only.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 27 4.6 electrical requirements the following section provides information on the electrical requirements for the celeron processor mobile module mmc-2. 4.6.1 dc requirements table 17 provides dc power supply design criteria. table 17 . power supply design specifications 1 symbol parameter min nom max unit notes v dc dc input voltage 5.0 12.0 21.0 v i dc 2,3 dc input current 0.1 0.9 3.5 a i dc-surge maximum surge current for v dc 17.3 a i dc-leakage 4 typical l eakage current for v dc 4.0 m a (at 25 c) v 5 power managed 5v voltage supply 4.75 5.0 5.25 v i 5 power managed 5v current 17 32 60 ma i 5-surge maximum surge current for v 5 0.6 a i 5-leakage typical leakage current for v 5 1.0 m a v 3 power m anaged 3.3v voltage supply 3.135 3.3 3.465 v i 3 power managed 3.3v current 0.8 1.2 2.0 a i 3-surge maximum surge current for v 3 2.8 a i 3-leakage typical leakage current for v 3 1.1 ma v cpupu processor i/o ring voltage 2.375 2.5 2.625 v 0.125 i cpupu 5 processor i/o ring current 0 10 20 ma v clk processor clock rail voltage 2.375 2.5 2.625 v 0.125 i clk 5 processor clock rail current 24.0 35.0 80 ma notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile processor frequencies. 2. v_dc is set for 12v in order to determine typical v_dc current. 3. v_dc is set for 5v in order to determine maximum v_dc current. 4. leakage current that can be expected when vr_on is deactivated and v_dc is still applied. 5. these values are system dependent.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 28 4.6.2 ac requirements table 18 shows the bclk ac requirements. table 18 . ac specifications at the processor core pins 1,2,3 t# parameter min nom max unit figure notes psb frequency 4 66.67 mhz all processor core frequencies t1: bclk period 4, 5 15.0 ns t2: bclk period stability 6, 7, 8 250 ps t3: bclk high time 5.3 ns at >1.8v t4: bclk low time 5.3 ns at <0.7v t5: bclk rise time 8 0.175 0.875 ns (0.9v-1.6v) t6: bclk fall time 8 0.175 0.875 ns (1.6v?0.9v) notes: 1. unless otherwise noted, all specifications in this table apply to all intel mobile modules. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00v at the processor core pins. 3. all ac timings for the cmos signals are referenced to the bclk rising edge at 1.25v at the processor core pin. all cmos signal timings (compatibility signals, etc.) are referenced at 1.25v at the processor core pins. 4. the internal core clock frequency is derived from the psb clock. the psb clock to core clock ratio is determined during initialization as described and is predetermined by the celeron processor mobile module mmc-2. 5. the bclk period allows a +0.5 ns tolerance for clock driver variation. see the ck97 clock synthesizer/driver specification for further information. 6. measured on the rising edge of adjacent bclks at 1.25v. the jitter present must be accounted for as a component of bclk skew between devices. 7. the clock driver?s closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the -20 db attenuation point, as measured into a 10-pf to a 20-pf load, should be less than 500 khz. this specification may be ensured by design characterization and/or measured with a spectrum analyzer. see the ck97 clock synthesizer/driver specification for further details. 8. not 100% tested. specified by design characterization as a clock driver requirement.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 29 4.6.2.1 psb clock signal quality specifications and measurement guidelines table 19 describes the signal quality specifications at the processor core for the psb clock (bclk) signal. figure 4 describes the sig nal quality waveform for the psb clock at the processor core pins. table 19 . bclk signal quality specifications at the processor core 1,5 t# parameter min nom max unit v1: bclk v il 2 0.7 v v2: bclk v ih 2 1.8 v v3: v in absolute voltage range 3 ?0.8 3.5 v v4: rising edge ringback 4 1.8 v v5: falling edge ringback 4 0.7 v bclk rising/falling slew rate 0.8 4 v/ns notes: 1. unless otherwise noted, all specifications in this table apply intel mobile modules. 2. bclk must rise/fall monotonically between v il,bclk and v ih, bclk. 3. this is the processor psb clock overshoot and undershoot specification for a 66-mhz psb operation. 4. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. 5. for proper signal termination, refer to the clocking guidelines in the mobile pentium a ii processor / 440bx agpset advanced platform recommend design and debug practices. v2 v1 v3 v3 t3 v5 v4 t6 t4 t5 figure 4 . bclk, tck, and picclk generic clock waveform at the processor core pins 4.7 voltage regulator the dc voltage regulator (dc/dc converter) provides the appropriate core voltage, the i/o ring voltage, and the sideband signal pullup voltage for the celeron processor mobile module mmc-2. the voltage range is 5 volts to 21 volts. 4.7.1 voltage regulator efficiency table 18 lists the voltage regulator efficiencies.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 30 table 20 . typical voltage regulator efficiency icore, a 3 v_dc, v i_dc, a 2 efficiency 1 1 5.0 0.370 82.8% 2 5.0 0.702 88.8% 3 5.0 1.044 89.8% 4 5.0 1.404 89.7% 5 5.0 1.762 88.1% 6 5.0 2.144 86.4% 7 5.0 2.528 85.0% 1 12.0 0.159 79.7% 2 12.0 0.295 87.0% 3 12.0 0.438 87.8% 4 12.0 0.584 87.3% 5 12.0 0.736 86.1% 6 12.0 0.890 84.9% 7 12.0 1.043 83.8% 1 21.0 0.091 79.3% 2 21.0 0.170 86.0% 3 21.0 0.253 87.3% 4 21.0 0.340 85.3% 5 21.0 0.429 84.1% 6 21.0 0.519 82.9% 7 21.0 0.617 80.7% notes: 1. these efficiencies will change with future voltage regulators that accommodate wider ranges of input voltages. 2. with v_dc applied and the voltage regulator off, typical leakage is 0.3 ma with a maximum of 0.7 ma. 3. icore indicates the cpu core current being drawn during test and measurement. 4.7.2 control of the voltage regulator the vr_on pin turns the dc voltage regulator on or off. the vr_on pin should be controlled as a function of the susb#, which controls the system?s power planes. vr_on should switch high only when the following conditions are met: v_5(s) => 4.5v and v_dc => 4.75v. caution - turning on vr_on prior to meeting these conditions will severely damage the celeron processor mobile module mmc-2 . the vr_pwrgd signal indicates that the voltage regulator power is operating at a stable voltage level. use vr_pwrgd on the system electronics to control power inputs and to gate pwrok to the piix4e/m. table 21 lists the voltage signal definitions and sequences, and figure 5 shows the signal sequencing and the voltage planes sequencing required for normal operation of the celeron processor mobile module mmc-2.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 31 4.7.2.1 voltage signal definition and sequencing table 21 . voltage signal definitions and sequences signal source definitions and sequences v_dc system electronics v_dc is required to be between 5v and 21v dc and is driven by the system electronics? power supply. v_dc powers the module?s dc-to-dc converter for the processor core and i/o voltages. the module cannot be hot inserted or removed while v_dc is powered on. v_3 system electronics v_3 is supplied by the system electronics for the 82433bx. v_5 system electronics v_5 is supplied by the system electronics for the 82433bx?s 5.0-v reference voltage and the module?s voltage regulator. vr_on system electronics vr_on is a 3.3-v (5v tolerant) signal that enables the module?s voltage regulator circuit. when driven active high the voltage regulator circuit is activated. the signal driving vr_on should be a digital signal with a rise and fall time of less than or equal to 1 m s. (vil (max)=0.4v, vih (min)=3.0v.) v_core (also a host bus gtl+ termination voltage vtt) module a result of vr_on being asserted, v_core is an output of the dc-dc regulator on the module and is driven to the core voltage of the processor. it is also used as the host bus gtl+ termination voltage, known as vtt. vr_pwrgd module upon sampling the voltage level of v_core (minus tolerances for ripple), vr_pwrgd is driven active high. if vr_pwrgd is not sampled active within 1 second of the assertion of vr_on, then the system electronics should deassert vr_on. after v_core is stabilized, vr_pwrgd will assert to logic high (3.3v). this signal must not be pulled up by the system electronics. vr_pwrgd should be ?anded? with v_3s to generate the piix4e/m input signal, pwrok. the system electronics should monitor vr_pwrgd to verify it is asserted high prior to the active high assertion of piix4e/m pwrok. v_cpupu module v_cpupu is 2.5v. the system electronics uses this voltage to power the piix4e/m-to-processor interface circuitry. v_clk module v_clk is 2.5v. the system electronics uses this voltage to power the hclk[0:1] drivers for the processor clock. the following list provides additional specifications and clarifications of the power sequence timing and figure 5 provides an illustration. 1. the vr_on signal may only be asserted to a logical high by a digital signal after v_dc 3 4.7 volts, v_5 3 4.5 volts, and v_3 3 3.0 volts. 2. the rise time and fall time of vr_on must be less than or equal to 1 microsecond when it goes through its vil to vih. 3. vr_on has its vil (max) = +0.4 volts and vih (min) = +3.0 volts. 4. the vr_pwrgd will get asserted to logic high (3.3 volts) after v_core is stabilized and v_dc reaches 5.0 volts. this signal should not and can not be pulled up by the system electronics. 5. in the power-on process, intel recommends to raise the higher voltage power plane first (v_dc), followed by the lower power planes (v_5, v_3), and finally assert vr_on after above voltage levels are met on all rails. the power-off process should be the reverse process, i.e. vr_on gets deasserted, followed by the lower power planes, and finally the higher power planes. 6. vr_on must monotonically rise through its vil to vih and fall through its vih to vil points. the sign of slope can not change between vil and vih in rising and vih and vil in falling. 7. vr_on must provide an instantaneous in-rush current to the module with the following values as listed in table 22.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 32 table 22 . vr_on in-rush current instantaneous dc operating max 41.0 ma 0.1 m a typ 0.2 ma 0.0 m a note: these values are based on a 3.3v vr_on signal. 8. vr_on valid-low time: this specifies how long vr_on needs to be low for a valid off before vr_on can be turned back on again. in going from a valid on to off and then back on, the following conditions must be met to prevent damage to the oem system or the intel mobile module: vr_on must be low for 1 millisecond. the original voltage level requirements for turn-on must be met before assertion of vr_on (i.e. v_dc 3 4.7 volts, v_5 3 4.5 volts, and v_3 3 3.0 volts). power sequence timing v_dc 1. pwrok on i/o board should be active on when vr_pwrgd is active and v_3s is good. 2. cpu_rst from i/o board should be active for a minimum of 6 ms after pwrok is active and pll_stp# and cpu_stp# are inactive. note that pll_stp# is an and condition of rsmrst# and susb# on the piix4e/m. 3. v_dc >= 4.7v, v_5>=4.5v, v_3s>=3.0v. 4. v_cpupu and v_clk are generated on the intel mobile module. 5. this is the 5v power supplied to the processor module connector. this should be the first 5v plane to power up. 6. vr_pwrgd is specified to its associated high/active by the module regulator within less than or equal to 6 ms max. after the assertion of vr_on. v_3 v_5 vr_pwrgd v_3s vr_on 0 ms min 0 ms min 0 ms min 6 3 v_cpupu/ v_clk 5 figure 5 . power-on sequence timing 4.7.3 power planes: bu lk capacitance requirements in order to provide adequate filtering and in-rush current protection for any system design, bulk capacitance is required. a small amount of bulk capacitance is supplied on the module. however, in order to achieve proper filtering, additional capacitance should be placed on the system electronics.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 33 table 23 details the bulk capacitance requirements for the system electronics. table 23 . capacitance requirement per power plane power plane capacitance requirements esr ripple current rating v_dc 100 uf, 0.1 uf, 0.01 uf 1 20 m w 1a-3.5a 3 20% tolerance at 35v v_5 100 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 10v v_3 470 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 6v v_3s 100 uf, 0.1 uf, 0.01 uf 1 100 m w n/a 20% tolerance at 6v vcc_agp 22 uf, 0.1 uf, 0.01 uf 1 100 m w 1a 20% tolerance at 6v v_cpupu 2.2 uf, 8200 pf 1 n/a n/a 20% tolerance at 6v v_clk2 10 uf, 8200 pf 2 n/a n/a 20% tolerance at 6v notes: 1. placement of above capacitance requirements should be located near the connector. 2. v_clk filtering should be located next to the system clock synthesizer. 3. ripple current specification depends on v_dc input. for 5.0-v v_dc, a 3.5a device is required. for v_dc at 18v or higher, 1a is sufficient.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 34 4.7.4 surge current guidelines this section provides the results of a worst case, surge current analysis. the analysis determines the maximum amount of surge current that the celeron processor mobile module mmc-2 can manage. in the analysis, the module has two 4.7 microfarads with an esr of 0.15 ohms each. the mmc-2 is approximately 30.0 milliohms of series resistance, for a total series resistance of 0.18 ohms. if powering the system with the a/c adapter (18 volts), the amount of surge current on the module would be approximately 100 amperes. this information is also used to develop i/o bulk capacitance requirements. see table 23 for more information. note : depending on the system electronics design, different impedances may yield different results. a thorough analysis should be performed to understand the implications of surge current on their system. figure 6 shows an electrical model used when analyzing instantaneous in-rush conditions, and figure 7 illustrates the results with a spice simulation. figure 6 . instantaneous in-rush current model
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 35 figure 7 . instantaneous in-rush current due to component height requirements ( 4 millimeters) of the celeron processor mobile module mmc-2, polymerized organic semiconductor capacitors must be used as input bulk capacitance in the voltage regulator circuit. because of the capacitor?s susceptibility to high in-rush current, special care must be taken. one way to soften the in-rush current and provide overvoltage and overcurrent protection is to ramp up v_dc slowly using a circuit similar to the one shown in figure 8.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 36 note: values shown are for reference only. figure 8 . overcurrent protection circuit 4.7.4.1 slew-rate control: circuit description in figure 8, pwr is the voltage generated by applying the ac adaptor or battery. m1 is a low rds (on) p-channel mosfet such as a siliconix* si4435dy. when the voltage on pwr is applied and increased to over 4.75 volts, the under_voltage_lockout circuit allows r4 to pull up the gate of m3 to start a turn-on sequence. m3 pulls its drain toward ground forcing current to flow through r2. m1 will not start to source any current until after t_delay with t_delay defined as: t_delay . . r2 c9 ln 1 vt vpwr vgs_max vgs_max . r16 r16 r2 vpwr the system manufacturer?s vgs_max specification of 20 volts must never be exceeded. however, vgs_max must be high enough to keep the rds (on) of the device as low as possible. after the initial t_delay, m1 will begin to source current and v_dc will start to ramp up. the ramp up time, t_ramp, is defined as: t_ramp . . r2 c9 ln 1 vsat vgs_max t_delay maximum current during the voltage ramping is: i . ctotal vpwr t_ramp with the circuit shown in figure 8: t_delay = 5.53 ms; t_tran = 14.0 ms; and i_max = 146 ma.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 37 figure 8 shows a spice simulation of the circuit in figure 7. to increase the reliability of tantalum capacitors, use a slew- rate control circuit described in figure 7 and voltage derate the capacitor about 50 percent. that is, for a maximum input voltage of 18.0 volts, use a 35.0-volt, low esr capacitor with high ripple current capability. place five, 22-microfarad/35- volt capacitors on the baseboard, directly at the v_dc pins of the processor module connector. finally, the slew-rate control circuit should be applied to every input power source to the system v_dc to provide the most protection. a potential problem still exists if all power sources are ?logically or?ed? together at the pwr node. for example, the system will immediately source current to the pwr node and v_dc if a 3x3 li-ion battery pack is powering the system (12.0 volts at pwr) and the ac adaptor (18.0 volts) is plugged into the system. this is because the slew-rate control is already on. therefore, the slew-rate control must be applied to every input power source to provide the most protection. figure 9 . spice simulation using in-rush protection (example only)) 4.7.4.2 undervoltage lockout: circuit description (v_uv_lockout) the circuit shown in figure 8 provides an undervoltage protection and locks out the applied voltage to the celeron processor mobile module mmc-2 to prevent an accidental turn-on at low voltage. the output of this circuit, pin 1 of the lm339 comparator, is an open collector output. it is low when the applied voltage at pwr is less than 4.75 volts. this voltage can be calculated with the following equation with the voltage across d7 as 2.5 volts (d7 is a 2.5-volt reference generator). v_uv_lockout . vref 1 r17 . r18 r25 r18 r25 = v_uv_lockout 4.757 volt 4.7.4.3 overvolt age lockout: circuit description (v_ov_lockout)
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 38 the celeron processor mobile module mmc-2 operates with a maximum input voltage of 21 volts. this circuit locks out the input voltage if it exceeds the maximum 21 volts. the output of this circuit, pin 14 of the lm339 comparator, is an open-collector output. it is low when the applied voltage at pwr is more than 21 volts. this voltage can be calculated with the following equation: v_ov_lockout . . vref r26 r26 r27 1 r24 r23 = v_ov_lockout 20.998 volt 4.7.4.4 overcurrent protection: circuit description figure 8 shows that the circuit detects an overcurrent condition and cuts off the input voltage applied to the celeron processor mobile module mmc-2. this circuit has two different current limit trip points, which accounts for the different maximum current drain by the celeron processor mobile module mmc-2 at different input voltages. assuming the ac adaptor is 18.0 volts and the battery is a 3x3 li-ion configuration with a minimum voltage of 7.5 volts, the maximum current for the above circuit can be calculated using the following expression: with ac adaptor (i_wadaptor): i_wadaptor . vref vbe_q1 r14 r13 r1 i_wadaptor = 0.989 amp without ac adaptor (i_woadaptor): i_woadaptor . vref vbe_q1 . r14 r33 r14 r33 r13 r1 i_woadaptor = 2.375 amp
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 39 4.8 active thermal feedback table 24 i dentifies the address allocated for the smbus thermal sensor used on the celeron processor mobile module mmc-2. table 24 . thermal sensor smbus address table function smbus address thermal sensor 1001 110 note: the thermal sensor used is compliant with smbus addressing. please refer to the pentium? ii processor thermal sensor interface specification . 4.9 thermal sensor configuration register the configuration register of the thermal sensor controls the operating mode (auto convert vs. standby) of the device. since the processor temperature varies dynamically during normal operation, auto convert mode should be used exclusively to monitor processor temperature. table 25 shows the format of the configuration register. if the run/stop bit is low, then the thermal sensor enters auto convert mode. if the run/stop bit is set high, then the thermal sensor immediately stops converting and enters the standby mode. the thermal sensor will still perform temperature conversions in standby mode when it receives a one-shot command. however, the result of a one-shot command during auto convert mode is not guaranteed. intel does not recommend using the one-shot command to monitor temperature when the processor is active, only auto convert mode should be used. refer to the mobile pentium ? ii processor and pentium ? ii processor mobile module thermal sensor interface specifications , rev.1.0. table 25 . thermal sensor configuration register bit name reset state function 7 msb mask 0 masks smbalert# when high. 6 run/stop 0 standby mode control bit. if low, the device enters auto- convert mode. if high, the device immediately stops converting, and enters standby mode where the one-shot command can be performed. 5 ? 0 rfu 0 reserved for future use. note: all rfu bits should be written as ?0? and read as ?don?t care? for programming purposes. 5.0 mechanical specification this section provides the physical dimensions for the celeron processor mobile module mmc-2. 5.1 module dimensions figure 10 shows the board dimensions and the connector orientation.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 40 figure 10 . board dimensions with 400-pin connector orientation
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 41 5.1.2 pin 1 location of the mmc-2 connector figure 11 shows the location of pin 1 of the 400-pin connector as referenced to the adjacent mounting hole. figure 11 . board dimensions with 400-pin connector- pin 1 orientation 5.1.3 printed circuit board thickness figure 12 shows the minimum and maximum thickness of the printed circuit board (pcb). the range of pcb thickness allows for different pcb technologies to be used with current and future intel mobile modules. note: the system manufacturer must ensure that the mechanical restraining method and/or system-level emi contacts are able to support this range of pcb for compatibility with future intel mobile modules. min: 0.90 mm max: 1.10 mm printed circuit board figure 12 . printed circuit board thickness
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 42 5.1.4 height restrictions figure 13 shows the mechanical stack-up and associated component clearance requirements. this is the module keep-out zone and should not be entered. the system manufacturer establishes board-to-board clearance between the module and the system electronics by selecting one of three mating connectors. the connector sizes available are 4 millimeters, 6 millimeters, and 8 millimeters. the three sizes provide flexibility in choosing the system electronics components between the two boards. information on these connectors can be obtained from your local intel representative. note : the topside component clearance is independent of the pcb thickness. figure 13 . keep-out zone 5.2 thermal transfer plate the ttp on the cpu and the 82433bx provides heat dissipation and a thermal attach point where a system manufacturer can attach a heat pipe, a heat spreader plate, or a thermal solution to transfer heat through the notebook system. see figure 14 and figure 15 for attachment dimensions from the thermal interface block to the ttp. when attaching the mating block to the ttp, a thermal elastimer or thermal grease should be used. this material reduces the thermal resistance. the thermal interface block should be secured with 2.0-millimeter screws using a maximum torque of 1.5 kg*cm to 2.0 kg*cm (equivalent to 0.147 n*m to.197 n*m). the thread length of the 2.00- millimeter screws should be 2.25-millimeter gageable thread (2.25-millimeters minimum to 2.80-millimeters maximum). the system manufacturer should use the exact dimensions for maximum contact area to the ttp to ensure that no
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 43 warpage of the ttp occurs. if warpage occurs, the thermal resistance of the module could be adversely affected. the ttp thermal resistance between the processor core to the system interface (top of the ttp) is less than 1 celsius per watt. figure 14 . thermal transfer plate (a)
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 44 figure 15 . thermal transfer plate (b) 5.3 module physical support 5.3.1 module mounting requirements three mounting holes are available for securing the module to the system base. see figure 9 for mounting hole locations. these hole locations and board edge clearances will remain fixed for all intel mobile modules. all three mounting holes should be used to ensure long term mechanical reliability and emi integrity of the system. the board edge clearance includes a 0.762-millimeter (0.030 inches) wide emi containment ring around the perimeter of the module. this ring is on each layer of the module pcb and is grounded. on the surface of the module, the metal is exposed for emi shielding purposes. the hole patterns also have a plated surrounding ring to use a metal standoff for emi shielding purposes. standoffs should be used to provide support for the installed module. the distance from the bottom of the module pcb to the top of the system electronics board with the connectors mated is 4.0 millimeters + 0.16 millimeters / -0.13 millimeters. however, the warpage of the baseboard can vary and should be calculated into the final dimensions of the standoffs used. all calculations can be made with the intel a mmc-2 standoff/receptacle height spreadsheet. information on this spreadsheet can be obtained from your local intel representative. figure 16 shows the standoff support hole patterns, the board edge clearance, and the dimensions of the emi containment ring. no components are placed on the board in the keep-out area.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 45 hole detail, 3 places 0.762 mm width of emi containment ring 1.27+/- 0.19 mm board edge to emi ring 2.54+/-0.19 mm keep-out area 3.81+/-0.19 mm board edge to hole centerline 3.81+/-0.19 mm 4.45 mm diameter grounded ring + 0.050 mm - 0.025 mm hole diameter 2.413 mm figure 16 . standoff holes, board edge clearance, and emi containment ring 5.3.2 module weight the celeron processor mobile module mmc-2 weighs approximately 50 grams. 6.0 thermal specification 6.1 thermal design power the power handling capability of the system thermal solution may be reduced to less than the recommended typical thermal design power (tdp) with the implementation of firmware/software control or ?throttling?, which reduces the cpu power consumption and dissipation. the typical tdp is the typical power dissipation under normal operating conditions at nominal v_core (cpu power supply) while executing the worst case power instruction mix. this includes the power dissipated by all of the relevant components. during all operating environments, the processor junction temperature, t j , must be within the specified range of 0 celsius to 100 celsius. 6.2 thermal sensor setpoint the thermal sensor implements the smbalert# signal described in the smbus specification. smbalert# is always asserted when the temperature of the processor core thermal diode or the thermal sensor internal temperature exceeds either the upper or lower temperature thresholds. smbalert# may also be asserted if the measured temperature equals either the upper or the lower threshold. table 26 . thermal design power specification symbol parameter typical notes tdp module module thermal design power 11.5 w module tdp = core, 82433bx, and voltage regulator. note: 1. during all operating environments, the processor temperature, t j must be within the specified range of 0 celsius to 100 celsius. 2. tdp module is a thermal solution design reference point for oem thermal solution readiness for total module power.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 46 7.0 labeling information all intel mobile modules are tracked in two ways. the first is by the product tracking code (ptc). intel uses the ptc label to determine the assembly level of the module. the ptc contains 13 characters and provides the following information. example: pmi40002001aa definition: aa - processor module = pm b - celeron processor mobile module mmc-2 = i ccc - speed identity = 400, 366, 333, and 300 dd - cache size = 01 (128k) eee - notifiable design revision (start at 001) ff - notifiable processor revision (start at aa) note: for other intel mobile modules, the second field (b) is defined as: celeron processor mobile module(mmc-1) = h figure 17 . product tracking information the second tracking method is by an oem generated software utility. four strapping resistors located on module determine its production level. if connected and terminated properly, up to 16 module-revision levels can be determined. an oem generated software utility can then read these id bits with cpu ids and stepping ids to provide a complete module manufacturing revision level. for current ptc and module id bit information, please refer to the latest intel mobile module product change notification letter which can be obtained from your local intel sales representative.
intel a celeron ? processor mobile module mmc-2 at 400 mhz, 366 mhz, 333 mhz, and 300 mhz 47 8.0 environmental standards the environmental standards are defined in table 27. table 27 . environmental standards parameter condition specification temperature non-operating -40 c to 85 c cycle operating 0 c to 55 c humidity unbiased 85% relative humidity at 55 c voltage v_5 5v 5% v_3 3.3v 5% shock non-operating half sine, 2g, 11 msec unpackaged trapezoidal, 50g, 11 msec packaged inclined impact at 5.7 ft/s packaged half sine, 2 msec at 36 in simulated free fall vibration unpackaged 5 hz to 500 hz 2.2 grms random packaged 10 hz to 500 hz 1.0 grms packaged 11,800 impacts 2 hz to 5 hz (low frequency) esd damage human body model non-powered test of the module only for non-catastrophic failure. the module is tested at 2 kv and then inserted in a system for functional test.

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